The disclosed invention is directed generally to hold-off circuits, and more particularly to a programmable hold-off circuit for integrated circuit output pins.
In integrated circuit design, hold-off is a commonly used technique by which an output of an integrated circuit is delayed for a fixed minimum period of time after the active clock transition in order to assure that the signal at the input of a receiving flip-flop is stable for a time interval that is equal to or exceeds the hold-time requirement of such receiving flip-flop. Hold-off is conventionally implemented in the hardware design of integrated circuit. However, where an integrated circuit is intended for use in multiple applications, there may be some applications where hold-off is required for particular outputs and some where hold-off is not required for outputs. This is due to the unique path delays and clock skews of the various applications. Since a fixed hold-off time adds to the propagation delay between registers, it is desirable to use hold-off only when necessary to assure sufficient hold time margin. Since hold-off is currently being implemented by hardware design, detailed analysis is required prior to finalizing the design of an integrated circuit in which hold-off is being implemented, and hold-off is probably being unnecessarily implemented as a conservative measure.